The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure containing silicon fins located on a buried oxide structure and having different heights, yet having topmost surfaces that are coplanar with each other. The present application also provides a method of forming such a semiconductor structure.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continue scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that metal oxide semiconductor transistors are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, silicon fin field effect transistors (FinFETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Silicon fin field effect transistors (FETs) can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
Double-gated FinFETs allow the scaling to continue for the next two to three generations. However, due to the three-dimensional nature of the device, the device width (in this case fin height) cannot be varied as desired. For example and in SRAM devices, the device width ratio for pull-up and pull-down FET devices is an important parameter. In conventional (i.e., planar) circuits, this ratio can be randomly chosen by the designers to benefit the circuits even with cell size constrains. However, the device width for FinFETs is determined by the number of fins (n Fins) times (X) the fin height (h Fin) and designers cannot use as many fins as they wish due to cell size (footprint) constrains, hence the FinFET device width ratio is limited in FinFET circuits.
In view of the above, the is a need to provide a semiconductor structure containing silicon fins having different heights, while maintaining a reasonable fin height to width ratio for process feasibility.